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Application Note 9814
Digital Loop Back Con?guration
J5
J6
J10
J4
JP3
J7
JP9
J8
J9
JP7
J11
J3
HC55185
JP6
JP4
JP8
CODEC
APP CKT
J12
APP CKT
JP5
J13
J2
JP1
JP2
JP11
JP12
JP10
J14
J1
S1
0
S2
0
S3
1
S4
x
S5
1
S6
0
CLOCK GENERATION & MUX
J15
FIGURE 6. DIGITAL LOOP BACK CONNECTORS AND JUMPERS
Description
The digital loop back con?guration veri?es the interface and
operation of the HC55185 device and the CODEC. This
con?guration provides a self test to verify proper operation of
the board. In addition, it provides a complete digital loop,
Signal Flow
Driving a signal at VREC, J8, will result in a signal from the
CODEC receive output when the HC55185 device is
terminated at Tip and Ring. The following diagram shows the
signal path formed by the jumpers and terminated SLIC.
allowing analog control of the digital input and output of the
CODEC. Forward active and reverse active or teletax will
support the digital loop back con?guration.
VREC (J8)
JP4
Power Supply Connections
Power should be applied to the evaluation board using the
primary power cable. Either J5 or J6 may be used. Prior to
600 ?
TIP
VRX
PO-
DR
J14
applying power, the voltage setting of each supply should be
veri?ed. The power supplies should be turned off while
mating the primary power cable to the evaluation board.
VTX
RING
HC55185
JP6
-2
TG
DT
CODEC
Jumper Settings
All jumper settings and functions are described below.
TABLE 3. DIGITAL LOOP BACK JUMPER POSITIONS
JUMPER DESCRIPTION
FIGURE 7. DIGITAL LOOP BACK SIGNAL FLOW
With VREC input signal level of 0.775V RMS , a signal level of
0.337V RMS should result at the VTX output when terminated
with 600 ? . The signal level at VTX is determined by the
JP6
Connects the device transmit output VTX to the
CODEC amplifier for transhybrid balance.
4-wire to 4-wire gain, G 44 , of the HC55185. The transhybrid
balance is not connected, therefore, the digitized signal level
JP10, POSN 2 Sets the CODEC master clock to 512kHz.
at the CODEC will be approximately 0.674V RMS . The
CODEC transfer functions are set for unity gain, therefore
JP11
JP12
J14, POSN 1
Enables the on board logic multiplexer.
Inserting jumper selects on board clock and frame
sync generator.
Connects the CODEC digital output DT to digital
input DR.
the signal level at PO- should be approximately 0.674V RMS .
The signal levels for digital loop back are independent of the
clock selected by JP10.
Refer to the device electrical data sheet for the design
equations for the 4-wire to 4-wire gain as a function of
termination and synthesized impedance.
4-7
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